The invention relates to phase-locked loop type clock-signal generators that produce a high-frequency clock signal from a low-frequency clock signal. Among these generators, the invention relates more specifically to those using a digital oscillator producing clock signals whose period is proportional to a binary number received by the oscillator.
A prior art generator 10 according to FIG. 1 has a comparator 12, a binary number decoder 14 and a digital oscillator 20 that are series connected. An output of the oscillator 20 is connected to an input of the comparator 12. The generator 10 provides a high-frequency signal CKHF (with a period PHF) from a low-frequency reference signal CKBF (with a period PBF).
The comparator 12 has two inputs to which the high-frequency signal CKHF and the reference signal CKBF are applied. The comparator 12 compares the period PHF of the clock signal CKHF with a desired period PHF0. The desired period PHF0 is, for example, a multiple of the period PBF. At N serial outputs, the comparator 12 produces a number NR in the form of N=2N binary signals S(1), . . . , S(N) representing the bits of NR. The number NR has the following characteristics: NR increases if PHF less than PHF0, NR decreases if PHF greater than PHF0, otherwise NR is constant.
The binary signal decoder 14 has N inputs connected to the outputs of the comparator 12. The decoder 14 provides decoded binary clock signals SD(1), SD(2), . . . , SD(2N) at 2N serial outputs. These decoded binary signals indicate the value of the number NR given by the counting circuit: S(NR+1)=1, and S(i)=0 for all values of i ranging from 1 to 2N, and ixe2x89xa0NR+1.
The digital oscillator 20 receives the binary signals SD(1), SD(N), . . . , SD (2N) and produces the clock signal CKHF at a serial output OUT. The oscillator 20 is shown in FIG. 2. It comprises 2Nxe2x88x921 elementary cells A(1) to A(2Nxe2x88x921) that are identical, and one cell B that is different from the cells A(j), with j being an integer ranging from 1 to 2Nxe2x88x921. Each cell A(j), B comprises a data input e and a data output s.
The input e of the cell B is connected, first, to its output s by a switch INT(1) controlled by the signal SD(1) and, second, to the output of the cell A(1). The input of each cell A(1) to A(2Nxe2x88x922) is connected, first, to the output s of the cell B by a switch INT(2) to INT(2Nxe2x88x921) controlled by the signal SD(2) to SD(2Nxe2x88x921) and, second, to the output of the next cell A(2) to A(2Nxe2x88x921). The input of the cell B is connected to the output of the cell A(1), and the output of the cell A(2Nxe2x88x921) is connected to the output of the cell B by a switch INT(2N) controlled by the signal SD(2N). The switch INT(i), with i ranging from 1 to 2N, is closed when the signal SD(i) is active. If not it is open.
The output of the cell B is the output OUT of the oscillator 20 at which the high-frequency CKHF is given. The cell B comprises an odd number NB of series connected primary inverters, with NBxe2x89xa71. The output of the first inverter is connected to the output of the cell B, and the input of the NBth inverter is connected to the input e of the cell B. The cell B is equivalent to an inverter whose propagation times (downward propagation time TB0 and upward propagation time TB1xe2x89xa0TB0) are greater than the propagation times of the primary inverters that form it.
Since all the cells A(1) to A(2Nxe2x88x921) are identical, only the first cell A(i=1) is described in detail in FIG. 2. The first cell comprises an even number NA of identical primary inverters (in the example of FIG. 2, NA=2) series connected with a switch INTA(i=1) controlled by the signal SD(i=1) by an inverter. The input of the last inverter is connected to the input of the cell A(1), and the output of the switch INTA(1) is connected to the output of the cell A(1). The switch INTA(1) is open when SD(1) is active. If not it is closed.
The switch INTA(1) is necessary for isolating the primary inverters from one another. Without the presence of the switch INTA(1), the output of an inverter of the cell A(1) and the output of an inverter of the cell B would be short-circuited at the closing of the switch INT(1).
A cell A(1) to A(2Nxe2x88x921) comprises a number NA of inverters. It is equivalent to a delay circuit. The cell transmits the signal that it receives at its input to its output, after a period of time TA0 if the signal is equal to 0, or after a period of time TA1 if the signal is equal to 1. The propagation times TA0, TA1 are different from each other because the propagation time of a 0 in a switch INTA is different from the propagation time of a 1 in the same switch.
The clock signal generator 10 works as follows. The comparator 12 provides a number NR ranging from 0 to 2Nxe2x88x921 and produces an associated signal SD(NR+1)=1, with the other signals SD(ixe2x89xa0NR+1) being all zero signals. The switch INT(NR+1) controlled by the signal SD(NR+1) closes and the switch INTA(NR+1) opens. NR cells A are selected to form, with the cell B, a looped chain of cells A, B in the oscillator 20.
The propagation time of a 0 between the input and the output of the chain of cells is equal to T10=NR*TA0+TB1, and the propagation time of a 1 between the input and output of the chain of cells is equal to T11=NR*TA1+TB0. The period PHF of the high-frequency signal CKBF obtained at the output OUT of the oscillator is equal to PHF=T10+T11=NR*(TA1+TA0)+(TB1+TB0). It is therefore proportional to NR.
If the period obtained PHF is smaller than the desired period PHF0, then the number NR is increased by the comparator 12 to increase the number of cells A in the chain of cells, and thus increase the period PHF of the signal CKHF. Conversely, if the signal obtained PHF is greater than the desired period PHFO, then the number NR is diminished by the comparator 12 to diminish the number of cells A in the loop, and thus reduce the period of CKHF.
In other words, in the oscillator 20, the total number of cells, and therefore the total number of inverters in the chain of cells, varies as a function of the number NR given by the comparator 12, and the period PHF of the clock signal obtained is proportional to NR. The total number of inverters in the chain, however, must be an odd number in order that there may be oscillations.
Furthermore, when NR increases (or decreases) by one, a cell A is added (or eliminated) in the chain. It may be recalled that a cell A comprises an even number NA of inverters and a switch INTA.
The minimum variation of the period of a signal CKHF produced by the oscillator 20 defines the uncertainty on the period of the signal CKHF, in other words, the precision of the oscillator. For the oscillator 20, the uncertainty on the period is therefore equal to TA0+TA1, with TA0 and TA1 being the propagation time of a 0 and a 1 in a cell A comprising an even number of inverters and a switch INTA.
By way of an indication, exemplary embodiments of switches INT(1), . . . , INT(2N) and primary inverters used in the cells A(1), . . . , A(2Nxe2x88x921), B are shown in FIGS. 3a and 3b. When a switch has to be series connected with an inverter, as is the case in the cells A(1), . . . , A(2Nxe2x88x921), then these two elements are preferably made in the form of a single circuit like that of FIG. 3c, which shows an inverter switch.
A first problem of signal generators such as that of FIG. 1 is the large size of these circuits. The decoders include a set of at least 2N logic gates, with at least one per binary signal SD(i) being produced. The decoders thus become bulky very soon when the number n rises.
A second problem of existing generators is related to the construction of inverter-based oscillators. All the cells A(1), . . . , A(2nxe2x88x921), B are physically linked to the output point S of the oscillator 20, directly or by a switch. Thus, the parasitic capacitance at this point is very high, due to the cells themselves, the switches and the connecting wires between the elements of the circuit. This capacitance leads to parasitic oscillations, for example, when two switches placed side by side switch simultaneously. These oscillations can result in errors in the oscillator 20, for example, when there is an unwanted conversion of a 0 to a 1.
A third problem lies in the fact that the cycle ratio of the signal CKHF obtained, equal to the time during which the signal is in the high state divided by the period of the signal, is different from xc2xd.
Due to the presence of a switch INT(i) and an even number NA of inverters in the cell A(i), the propagation time T10 of a 0 and the propagation time T11 of a 1 in the chain of cells are substantially different from each other. Thus, the cycle ratio of the signal CKHF obtained, which is equal to T11/PHF=T11/(T10+T11), is different from xc2xd.
In view of the foregoing background, an object of the invention is to provide a small-sized clock signal generator while preferably eliminating the decoder, which is generally used in this type of circuit.
Another object of the invention is to provide a clock signal generator having a parasitic capacitance distributed throughout the circuit, which is no longer concentrated at the output of the oscillator.
Yet another object of the invention is to provide a generator that produces substantially perfect clock signals, and preferably having a cycle ratio equal to xc2xd.
These and other objects, advantages and features according to the invention are provided by a generator comprising an oscillator producing a clock signal from N logic signals representing an N-bit control number, with N being an integer greater than 1.
According to the invention, the oscillator comprises N+1 components. Each of the N most significant components are assigned a place value i, with i ranging from 1 to N. The least significant component gives the clock signal, and at least one component (C(i)) with a place value i greater than 1 comprises first and second arms. The first arm comprises, connected in series, a cell and a first switch controlled by the logic signal with a place value i. The first switch is open when the logic signal with the place value i is active. The second arm comprises, connected in series, cells and a second switch controlled by the logic signal with a place value i. The second switch is closed when the logic signal with the place value i is active.
Thus, the oscillator of the generator of the invention makes direct use of the N binary signals produced by the comparator as will be seen more clearly below. The decoder of the prior art circuit is therefore eliminated.
Furthermore, every common point of the oscillator is connected to a small number of components. For example, the input of the component with a place value I is connected only to the two arms of the component with the place value I, and to the two arms of the component with the place value I+1. Consequently, the parasitic capacitance of the oscillator is thus distributed throughout the elements of this circuit, and there is no longer any excessively capacitive point, which is a source of error.
Preferably, the second arm of the component with the place value i comprises a number of cells equal to 2i+1. This number is an odd number. Consequently, two adjacent cells of the second type constantly receive opposite logic signals and the cycle ratio of the high-frequency signal, obtained with a generator of the invention, is equal to xc2xd, as shall be seen more clearly below.
Preferably, the least significant component comprises an even number of inverters if N is an odd number, or an odd number of inverters if N is an even number. Preferably again, each cell comprises an odd number of series connected inverters. Consequently, regardless of the value of the number NR, the total number of inverters in the chain of cells is always an odd number. The oscillations are therefore always possible. Each cell may also comprise a switch series connected with the inverters. The output of each cell can thus be isolated from the output of any other cell if necessary.
According to a preferred embodiment, the oscillator also comprises means to apply a precharging signal to the cells of the first and second arms of the component with the place value i. For the component with the place value i, the precharging signal is either the clock signal or the signal applied to an input of the component with a place value i.
A generator according to the invention comprises, in addition to an oscillator such as the one described above, a comparator to compare the period of the clock signal with a desired period and provide an N-bit control number in the form of N logic signals. The control number varies as follows. The control number increases if the period of the clock signal is smaller than the desired period. The control number decreases if the period of the clock signal is greater than the desired period, and if not, the control number is constant.